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IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 1/13 FEATURES E E E E E E E E E E E E E Fast flash converter Integrated glitch filter; minimum transition distance can be set using the optional resistor Selectable resolution of up to 64 steps per cycle and up to 16-fold interpolation Integrated instrumentation amplifiers with adjustable gain Direct connection of sensor bridges, no external components required 200 kHz input frequency with the highest resolution Incremental A QUAD B output of up to 3.2 MHz Reversed A/B phase selectable Index signal processing with half cycle index output Sensor bridge calibration supportable by analog/digital test signals Low power consumption from single 5 V supply TTL- /CMOS-compatible outputs Inputs and outputs protected against destruction by ESD APPLICATIONS E E E Angle interpolation from orthogonal sinusoidal input signals Linear and rotary encoders MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright (c) 2005, 2009 iCHaus
www.ichaus.com
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 2/13 DESCRIPTION iC-NV is a monolithic A/D converter which produces two digital A/B incremental signals phase-shifted at 90 from two sinusoidal input signals, also phase-shifted at 90. The converter operates on the flash principle with fast single comparators. The back-end signal processing circuit includes a no-delay glitch filter which can be set so that only clearly countable incremental signals are generated. The minimum transition distance for outputs A and B can be set via an external resistor and adapted to suit the application on hand. For static input signals hysteresis prevents the switching of the outputs. By programming the pins the interpolator can be set to nine different resolutions between 4 and 64 angle steps per cycle; multiplication values of between 1 and 16 are possible for the frequency. The phase relation between the sine/cosine input signals and the A/B incremental signals generated can be selected here. The device also incorporates an index signal processing circuit which generates a digital zero pulse at Z (gated with A only, respectively B) dependent on the analog sine/cosine input signals and the enable input ZERO. Alternatively, the converter MSB can also be output at Z for synchronization purposes in an absolute measuring system. The input amplifiers are configured as instrumentation amplifiers and permit sensor bridges to be directly connected without the need for external resistors. The input amplification has nine selectable settings which have been graded to suit standard sensor signals of between ca. 10mVpk and 1Vpk. If external calibration of the sensor bridge is required, eg. with regard to offset, various test functions can be activated. By this the amplified analog input signals come available at the outputs, for instance.
PACKAGES TSSOP20 to JEDEC Standard PIN CONFIGURATION TSSOP20 4.4mm
(top view)
PIN FUNCTIONS
No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PCOS NCOS SG1 SG0 VREF ROT SF1 SF0 GND Z (MSB) B A VDD RCLK VCC GNDA PZERO NZERO PSIN NSIN Function Input Cosine % Input Cosine & Gain Select Input Gain Select Input Reference Voltage Output A/B Phase Selection Input / Test Signal Output Resolution Selection Input / Test Signal Output Resolution Selection Input / Test Signal Output Ground (digital) Index Signal Output Z (MSB Output when ROT= open) / Test Signal Output Incremental Output B / Test Signal Output Incremental Output A / Test Signal Output +5 V Supply Voltage (digital) Min. Transition Distance Preset Input (use is optional; can be wired to VCC) +5 V Supply Voltage (analog) Ground (analog) Index Signal Enable Input % Index Signal Enable Input & Input Sine % Input Sine &
S6 S5 S4 S3 S2 S1
External connections linking VCC to VDD and GND to GNDA are required.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 3/13 ABSOLUTE MAXIMUM RATINGS
Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Supply Voltage analog Supply Voltage digital Voltage at NSIN, PSIN, NCOS, PCOS, NZERO, PZERO, SG1, SG0, RCLK SF1, SF0, ROT, A, B, Z Current in VCC Current in VDD Current in GND Current in NSIN, PSIN, NCOS, PCOS, NZERO, PZERO, SG1, SG0, VREF, RCLK, SF1, SF0, ROT, A, B, Z Pulse Current in all pins (Latch-up strength) ESD Susceptibility at all pins Operating Junction Temperature Storage Temperature Range Ta = 25 C, pulse duration 10 ms, VCC = VCCmax, VDD = VDDmax, Vlu() = (-0.5...+1.5) x Vpin()max HBM, 100 pF discharged through 1.5 k -40 -40 V() < VCC + 0.3 V V() < VDD + 0.3 V Conditions Fig. Min. G001 VCC G002 VDD G003 Vpin() -0.3 -0.3 -0.3 Max. 6 6 6 V V V Unit
G004 Imx(VCC) G006 Imx(VDD) G007 Imx(GND) G008 Imx()
-50 -50 -50 -50 -10
50 50 50 50 10
mA mA mA mA mA
G005 Imx(GNDA) Current in GNDA
G009 Ilu()
-100
100
mA
EG1 Vd() TG1 Tj TG2 Ts
2 150 150
kV C C
THERMAL DATA
Operating Conditions: VCC= VDD= 5V 10% Item T1 Symbol Ta Parameter Operating Ambient Temperature Range (extended range of -40 to +125 C on request) Conditions Fig. Min. -25 Typ. Max. 85 C Unit
All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 4/13 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC= VDD= 5V 10%, Tj= -40..125C, unless otherwise noted Item Symbol Parameter Conditions Tj C Total Device 1 2 3 4 5 6 7 VCC, VDD I(VCC) I(VDD) Von Voff Vhys Vc()hi Permissible Supply Voltage Supply Current in VCC Supply Current in VDD Power-On Reset Threshold Power-Down Reset Threshold Power-On Reset Hysteresis Clamp Voltage hi at NSIN, PSIN, NCOS, PCOS, NZERO, PZERO, SG1, SG0, ROT, SF1, SF0, VREF, RCLK Clamp Voltage lo at NSIN, PSIN, NCOS, PCOS, NZERO, PZERO, SG1, SG0, ROT, SF1, SF0, VREF, RCLK, A, B, Z Clamp Voltage hi at A, B, Z Input Offset Voltage Vc()hi= V() -VCC; I()= 1mA, other pins open fin()= 200kHz; A, B, Z open fin()= 200kHz; A, B, Z open 2 1 0.4 0.3 4.5 5.5 15 5 3.8 2.2 1.8 1.6 V mA mA V V V V Fig. Min. Typ. Max. Unit
8
Vc()lo
I()= -1mA, other pins open
-1.5
-0.3
V
9
Vc()hi
Vc()hi= V()-VDD; I()= 1mA, other pins open Vin() see table gain select GAIN= 10..66 GAIN= 3..7.1 V()= 0V.. VCC GAIN following table gain select GAIN following table gain select GAIN= 66.667 GAIN= 3.03 GAIN= 66.667 GAIN= 3.03 referred to 360 input signal, GAIN= 3.03; VPin= 2...2.6 Vpp, VNin= 2.5 Vdc VPin= 1...1.3 Vpp, VNin= 2.5 Vdc referred to period of A, B GAIN= 3.03 I(VREF)= -1mA..+1mA DIV= 1 (IPF= 10, 12, 16) DIV= 2 (IPF= 5, 8) DIV= 4 (IPF= 3, 4) DIV= 8 (IPF=2) DIV= 16 (IPF= 1) R(RCLK, GNDA)= 47K 1%; DIV= 1 DIV= 16 V(RCLK)= VCC; DIV= 1 DIV= 16 4 2 7
0.3
1.6
V
Input Amplifiers NSIN, PSIN, NCOS, PCOS 101 Vos() -7 -10 -50 95 98 500 2.3 10 15 7 10 50 101 102 mV mV nA % % kHz MHz V/s V/s
102 103 104 105 106
Iin() G() Grel fhc SR
Input Current Gain Gain Ration SIN/COS Cut-off Frequency Slew Rate
Signal Processing: Converter Accuracy 201 AAabs Absolute Angle Accuracy
-1 -2 -10
1 2 10
DEG DEG %
202 VREF 401 501
AArel
Relative Angle Accuracy
V(VREF) Reference Voltage at VREF RCLK Permissible Resistor at RCLK vs. GNDA
48 47 23 12 6 3 45 490 30 420
52 500 500 500 500 500 78 1000 78 1000
%VCC k k k k k ns ns ns ns
Signal Processing: Transition Distance Control
502
DT()
Minimum Transition Distance
503
DT()
Minimum Transition Distance
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 5/13 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC= VDD= 5V 10%, Tj= -40..125C, unless otherwise noted Item Symbol Parameter Conditions Tj C Zero Comparator 701 702 703 704 801 802 803 804 Vos() Iin() Vcm() Vdm() Vt()hi Vt()lo V0() Ri() Input Offset Voltage Input Current Common-Mode Input Volt. Range Differential Input Voltage Range Input Threshold Voltage hi Input Threshold Voltage lo Mid Level Voltage Input Resistance Saturation Voltage hi Saturation Voltage lo Rise Time Fall Time Vs()hi= VDD-V(); I()= -4mA I()= 4mA CL()= 50pF CL()= 50pF V()= Vcm() V()= 0V.. VCC -20 -50 1.4 0 60 25 43 45 150 20 50 VCC-1.5 VCC 78 40 57 220 0.4 0.4 60 60 mV nA V V %VCC %VCC %VCC k V V ns ns Fig. Min. Typ. Max. Unit
Signal Processing: Inputs SG1, SG0, ROT, SF1, SF0
Signal Processing: Outputs A, B, Z D01 Vs()hi D02 Vs()lo D05 tr() D06 tf()
ELECTRICAL CHARACTERISTICS: Diagrams
Fig. 1: Adjusting the minimum transition distance via resistor RCLK (given typical at 5V, 27C; for IPF= 1 within 5V 10% and -40..+125C ranges).
Fig. 2: Similar to Figure 1; the minimum transition distance can be reduced by smaller resistors RCLK.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 6/13
Fig. 3: Adjusting the minimum transition distance via resistor RCLK.
Fig. 4: Similar to Figure 3; minimum transition distance for smaller RCLK resistor values.
Fig. 5: Temperature drift of the minimum transition distance versus 27C (VDD= 5V).
Fig. 6: Temperature drift of the reduced minimum transition distance versus 27C (VDD= 5V).
Fig. 7: Definition of the relative angle accuracy.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 7/13 DESCRIPTION OF FUNCTIONS Input Amplifiers Input stages SIN and COS are configured as instrumentation amplifiers. The gain is dependent on the amplitude of the input signal and set via pins SG0 and SG1 according to the following table. So that the DC level to be adjusted half of the supply voltage is available at VREF. GAIN SELECT
Sine/Cosine Input Signal Levels Vin() Amplitude SG1 hi hi hi open open open lo lo lo SG0 hi open lo hi open lo hi open lo Gain 66.667 50.000 33.333 20.000 14.300 10.000 7.125 4.000 3.030 differential up to 60mVpp up to 80mVpp up to 120mVpp up to 0.2Vpp up to 0.28Vpp up to 0.4Vpp up to 0.56Vpp up to 1Vpp up to 1.3Vpp single ended up to 120mVpp up to 160mVpp up to 240mVpp up to 0.4Vpp up to 0.56Vpp up to 0.8Vpp up to 1.1Vpp up to 2Vpp up to 2.6Vpp Average value (DC) differential 0.7V .. VCC-1.2V 0.7V .. VCC-1.2V 1.2V .. VCC-1.2V 1.2V .. VCC-1.2V 0.7V .. VCC-1.3V 1.2V .. VCC-1.3V 1.2V .. VCC-1.4V 1.2V .. VCC-1.6V 1.2V .. VCC-1.7V single ended 0.7V .. VCC-1.2V 0.7V .. VCC-1.2V 1.2V .. VCC-1.3V 1.2V .. VCC-1.3V 0.8V .. VCC-1.4V 1.3V .. VCC-1.5V 1.4V .. VCC-1.7V 1.6V .. VCC-2.1V 1.8V .. VCC-2.4V
Converter Core, Transition Distance Control For each of the 64 comparator levels the sine/cosine input signals are calculated according to the theorem of addition and are fed into single comparators. This procedure guarantees a very high converter frequency yet also means that consecutive comparators can switch in a very short space of time in the event of input signal disturbances. The comparator outputs are thus fed into a transition distance control unit. This monitors the temporal sequence of the switching operations in such a way that each event is delayed by the length of the settable minimum gap to the previous event. If no errors arise the transitions pass the control unit without a time delay. Synchronization with a fixed clock pulse does not occur. The minimum transition distance is set via an external resistor positioned between RCLK and GNDA. Alternatively, pin RCLK can be shorted to VCC. Depending on the resolution maximum input frequencies of at least 200kHz are then guaranteed (see table of resolution).
Digital Processing Unit The transition distance control unit is followed by the digital processing unit. This is where the transition events are converted into a pulse sequence for the incremental outputs A and B. The square-wave signals generated have a phase shift of +90 or -90, depending on the direction of rotation. The phase relation between the sine/cosine input signals and the A/B output signals can be set using programming pin ROT. Alternatively, the MSB of the converter can be output to Z when ROT is high. With the zero signal this changes to high and has the pulse length of half a cycle. This signal can be used to synchronize the high-order tracks of an absolute-value encoder device.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 8/13 A/B OUTPUT PHASE SELECTION
ROT lo lo open open hi hi Input signals positive; COS leading SIN negative; SIN leading COS positive; COS leading SIN negative; SIN leading COS positive; COS leading SIN negative; SIN leading COS Output signals A, B; Z B leading A; Z A leading B; Z B leading A; MSB A leading B; MSB A leading B; Z B leading A; Z
Resolution, frequency ranges Nine different resolutions or interpolation factors (IPF) can be programmed via inputs SF0 and SF1. Resolutions 16, 12 and 10 are generated at the core of the converter itself. Resolutions of less than 10 are produced by division DIV in the digital processing unit. The minimum transition distance at outputs A and B corresponds to that of the transition distance control multiplied by the divisor of the digital processing unit. The minimum output transition distance (maximum output frequency) should be adjusted to tarry with the overall system (bandwidth of the transfer medium, sampling rate of the counter). The maximum input frequency is determined by the transition distance control and the resolution of the converter core (16, 12 or 10). This frequency can be increased for resolutions of less than 10 with an external resistor at RCLK. The following table gives possible settings.
RESOLUTION
SF1 SF0 IPF DIV internal division 1 1 1 2 2 4 4 8 16 finMAX finMAX for RCLK= VCC or RCLK= 47 k 200 kHz 260 kHz 320 kHz 200 kHz 320 kHz 200 kHz 260 kHz 200 kHz 200 kHz
hi hi hi open open open lo lo lo
hi open lo hi open lo hi open lo
16 12 10 8 5 4 3 2 1
200 kHz, RCLK= 47 k 260 kHz, RCLK= 47 k 320 kHz, RCLK= 47 k 400 kHz, RCLK= 23 k 640 kHz, RCLK= 23 k 800 kHz, RCLK= 12 k 1.04 MHz, RCLK= 12 k 1.6 MHz, RCLK= 6 k (3.2 MHz), RCLK= 3 k
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 9/13 Hysteresis iC-NV has an angular hysteresis which is independent of the input amplitude and phase. It prevents the outputs from switching when the inputs are static. The following diagram shows the effect this has with an interpolation factor of 8.
Fig. 8: Effect of angle hysteresis When the direction of rotation is reversed the integrated hysteresis circuit prompts the change in direction to be signaled at the outputs; the hysteresis causes a delay here. According to the resolution the hysteresis is set to one of the following fixed values. ANGLE HYSTERESIS
Interpolation factor Hysteresis DEG referred to A/B period 1 5.625 1/64 2 5.625 1/32 3 7.5 1/16 4 5.625 1/16 5 9 1/8 8 5.625 1/8 10 9 1/4 12 7.5 1/4 16 5.625 1/4
Zero pulse One zero pulse (index) is generated per cycle from the sine/cosine inputs. To be output to Z it must be enabled by the comparator at differential inputs PZERO and NZERO. The width of the zero pulse is half the length of the A and/or B signal output cycle. When Z is high, simultaneously A is high. The position of the zero pulse dependent on the interpolation factor and the direction of rotation is given in the following table.
INDEX WIDTH and POSITION
IPF 16 12 10 8 5 4 3 2 1 Z Width 11.25 15 18 22.5 36 45 60 90 180 Z Position with positive direction of rotation 45.. 56.25 45.. 60 45.. 63 39.375.. 61.875 36 .. 72 33.75 .. 78.75 30.. 90 22.5 .. 112.5 0 .. 180 Z Position with negative direction of rotation 33.75 .. 45 30 .. 45 27 .. 45 22.5 .. 45 9 .. 45 5.625 .. 50.625 (?) -7.5 .. 52.5 (?) -28.125 .. 61.875 (?) 354.375 .. 174.625
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 10/13 Oscilloscope diagrams The following diagrams give the input and output signals for various directions of rotation and ROT settings for interpolation factors 1 and 16.
Fig. 9: ROT= lo/open, COS leading SIN
Fig. 10: ROT= lo/open, SIN leading COS
Fig. 11: ROT= hi, COS leading SIN
Fig. 12: ROT= hi, SIN leading COS
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 11/13 Test functions Device iC-NV features internal test functions which can be used to ease sensor bridge calibration procedures if such are required. To enable test operation, a threshold current of approx. 1mA present at pin RCLK must be exceeded during power up. Subsequently, four different test modes are selectable starting with mode 3 set initially.
Fig. 13: Activating test functions via pin RCLK.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 12/13 Description of test signals MODE 3 ZK un-gated index/zero comparator output EXKA all comparators EXOR-gated SIN, NSIN, COS, NCOS amplifier outputs (signal valid with no load only) MODE 0 KA(0) Comparator 0-180 Duty cycle indicates offset of sine signal. KA(16) Comparator 90-270 Duty cycle indicates offset of cosine signal. KA(X): KA(8) EXOR KA(24) Comparator 45-225 Duty cycle indicates amplitude ratio of sine/cosine signal. Offset calibration must be performed first. MODE 1 CLK, UP, DN Control signals for external counters. MODE 2 NENOS, CLK, DALL Test signals for iC-Haus device test.
Test Mode 3 0 1 2
S1 (A) ZK KA(0) CLK NENOS
S2 (B) EXKA KA(16) UP CLK
S3 (Z) SIN KA(X) DN DALL
S4 (SF0) NSIN
S5 (SF1) COS
S6 (ROT) NCOS
APPLICATIONS INFORMATION Please refer to the applications information given with the iC-NV data sheet.
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (HannoverMesse). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
IC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 13/13 ORDERING INFORMATION
Type IC-NVH
Package TSSOP20 4.4mm
Order designation IC-NVH TSSOP20
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel +49-6135-9292-0 Fax +49-6135-9292-192 http://www.ichaus.com E-mail sales@ichaus.com
Appointed local distributors: http://www.ichaus.de/support_distributors.php

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